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NXP Semiconductors /MIMXRT1064 /PGC /CPU_PUPSCR

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Interpret as CPU_PUPSCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SW0SW2ISO

Description

PGC CPU Power Up Sequence Control Register

Fields

SW

There are two different silicon revisions: 1
SW2ISO

There are two different silicon revisions: 1

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data